Embodiments of the invention relate generally to integrated circuit packages and, more particularly, to an apparatus and method of fabricating a pre-fabricated electrical interconnect for an integrated circuit package.
As integrated circuits become increasingly smaller and yield better operating performance, packaging technology for integrated circuit (IC) packaging has correspondingly evolved from leaded packaging to laminated-based ball grid array (BGA) packaging and eventually to chip scale packaging (CSP). Advancements in IC chip packaging technology are driven by ever-increasing needs for achieving better performance, greater miniaturization, and higher reliability. New packaging technology has to further provide for the possibilities of batch production for the purpose of large-scale manufacturing thereby allowing economy of scale.
A standard CSP manufacturing process typically begins with placement of one or more dies onto a top surface of a silicon IC substrate. A plurality of redistribution layers are then deposited onto the IC substrate and the die(s) and are patterned to form a thin-film metal re-routing and interconnection system. The redistribution layers are typically formed from a benzocyclobutene (BCB) or polyimide material, for example, and applied via a spin-on or lamination application process. The electrical connection between the laminate re-distribution layers and the die(s) form an input/output (I/O) system to and from the die(s).
Advancements in IC packaging requirements pose challenges to the existing embedded chip build-up process. That is, it is desired in many current embedded chip packages to have an I/O system that provides inputs and outputs to both sides of the final IC package. In order to achieve this doubled-sided I/O system, electrical interconnections to the die(s) must be routed around the die(s) to the top and bottom surfaces of the IC package.
Several different methods have been developed to form a double-sided I/O system. For example, multiple lamination or re-distribution layers may be applied to the IC substrate to achieve the desired I/O system. However, the process of applying redistribution layers in a layer-by-layer fashion can lead to warpage in the rerouting and interconnection system, requiring the use of a molded epoxy stress balance layer or metal stiffener to maintain a flat or planer IC package.
Furthermore, due to the small size and complexity of IC packages, the process for fabricating IC packages is typically expensive and time consuming. Addition additional re-distribution layers to create the desired double-sided I/O system increases the number of processing steps, further increasing the cost and complexity of the manufacturing process.
Accordingly, there is a need for a simplified method for fabricating a double-sided I/O system for IC packages. There is a further need for a method for integrating double-sided I/O systems in IC packages while maintaining the flatness of the IC package.
It would therefore be desirable to have an apparatus and method of fabricating a pre-fabricated electrical interconnect for an integrated circuit package.